The damascene fabrication method and the introduction of low-K dielectrics
present a host of reliability challenges to Cu interconnects and
fundamentally change the mechanical stress state of Cu lines. In order to
capture the effect of individual process steps on the stress evolution in
the BEoL (Back End of Line), a process-oriented finite element modeling
(FEM) approach was developed. In this model, the complete stress history at
any step of BEoL can be simulated as a dual damascene Cu structure is
fabricated. The inputs to the model include the temperature profile during
each process step and materials constants. The modeling results are verified
in two ways: through wafer-curvature measurement during multiple film
deposition processes and with X-Ray diffraction to measure the mechanical
stress state of the Cu interconnect lines fabricated using 0.13um CMOS
technology. The Cu line stress evolution is simulated during the process of
multi-step processing for a dual damascene Cu/low-K structure. It is shown
that the in-plane stress of Cu lines is nearly independent of subsequent
processes, while the out-of-plane stress increases considerably with the
subsequent process steps.